Method of designing wiring structure of semiconductor device and wiring structure designed accordingly

ABSTRACT

A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ΔC/C or a resistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiring structure. The method sets a process-originated variation ratio (δ P ) for the wiring structure, a tolerance (ξ C ) for the capacitance variation ratio (ΔC/C), and a tolerance (ξ RC ) for the resistance-by-capacitance variation ratio (Δ(RC)/(RC)), evaluates a fringe capacitance ratio (F=C F /C P ) according to a fringe capacitance C F  and parallel-plate capacitance C P  of the wiring structure, and determines the wiring structure so that the fringe capacitance ratio (F) may satisfy the following: 
     
       
         
           
             
               
                 
                   
                     
                       
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     The method employs an equivalent-variations condition defined as |ΔC/C|=|Δ(RC)/(RC)| to determine the shape parameters of each wire of the wiring structure.

This is a division of application Ser. No. 09/602,253, filed Jun. 23,2000, now U.S. Pat. No. 6,978,434, which is incorporated herein byreference.

The entire contents of Japanese Patent Applications H11-180572 (filedJun. 25, 1999) and H11-269511 (filed Sep. 22, 1999) are incorporatedherein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to designing semiconductor devices, andparticularly, to a method of designing wiring structures of LSIs andwiring structures designed accordingly.

2. Description of the Related Art

To increase the scale of LSIs, fine technology for LSI elements isimproving. As LSI elements become smaller, process-originated variationsoccurring on LSI elements during, for example, patterning andion-implanting processes become not negligible in connection with thecharacteristics of LSIs. This is described in, for example, N. Shigyo etal., “Statistical simulation of MOSFETs using TCAD: Meshing noiseproblem and selection of factors,” Proc. IWSM98, p. 10, 1998.

One study based on sensitivity analyses about the influence ofprocess-originated variations on the characteristics of a circuit isdisclosed in Z. J. Lin and C. J. Sponos, “Sensitivity study ofinterconnect variation using statistical experimental design,” Proc.IWSM, p. 68, 1998. Another study based on analytic formulas is disclosedin O. S. Nakagawa et al., “Modeling of pattern-dependent on-chipinterconnect geometry variation for deep-submicron process and designtechnology,” Tech. Dig. IEDM, p. 137, 1997.

One of the important characteristics of an LSI is a delay time. Thedelay time of an LSI circuit is given by the product RC of theresistance R and capacitance C of wiring of the circuit if the wiring islong. If the wiring is short, the delay time of the circuit is theproduct RtrC of the transistor ON resistance Rtr and capacitance C ofthe wiring. This is described in H. B. Bakoglu and J. D. Meindl,“Optimal interconnection circuits for VLSI,” IEEE Trans. ElectronDevices, ED-32, p. 903, 1985. Namely, when considering characteristic ofwiring, an important factor to determine the delay of an LSI circuit isthe product RC of wiring of the circuit if the wiring is long, and it isthe capacitance C of the wiring if the wiring is short.

When forming an LSI with fine elements, it is necessary to reduce thecapacitance C and resistance-by-capacitance RC of wiring of the LSI. Itis also necessary to suppress a capacitance variation ratio ΔC/C andresistance-by-capacitance variation ratio Δ(RC)/(RC) caused byprocess-originated variations. There is a need for a wiring structurehaving suppressed C and AC as well as suppressed RC and Δ(RC)/(RC).

The prior arts merely analyze the influence of process-originatedvariations on circuit characteristics, and there is no prior art thatsuggests or provides a guideline for a wiring structure capable ofsuppressing variation ratios ΔC/C and Δ(RC)/(RC) caused byprocess-originated variations.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a method of designing awiring structure of a semiconductor device such as an LSI, capable ofsuppressing variations in the capacitance C or resistance-by-capacitanceRC of wiring of the semiconductor device caused by process-originatedvariations. Also provided are wiring structures based on the method.

In order to accomplish the objects, a first aspect of the presentinvention provides a method of designing a wiring structure of asemiconductor device. The method includes estimating aprocess-originated variation ratio (δ_(P)) for the wiring structure,setting a tolerance (ξ_(C)) for a capacitance variation ratio (ΔC/C) ofthe wiring structure, evaluating a fringe capacitance ratio(F=C_(F)/C_(P)) according to a fringe capacitance (C_(F)) andparallel-plate capacitance (C_(P)) of the wiring structure, anddetermining the wiring structure so that the fringe capacitance ratio Fmay satisfy the following:

$F \geq {\frac{\delta_{P}}{\xi_{C}} - 1}$

The wiring structure of the first aspect suppresses the ratio ΔC/Cwithin the tolerance ξ_(C).

If each wire in the wiring structure is shorter than 1 mm, the ratioΔC/C greatly affects the delay time, and therefore, the first aspect isespecially effective for semiconductor devices having such short wires.

A second aspect of the present invention provides a method of designinga wiring structure of a semiconductor device. The method includesestimating a process-originated variation ratio (δ_(P)) for the wiringstructure, setting a tolerance (ξ_(RC)) for a resistance-by-capacitancevariation ratio (Δ(RC)/(RC)) of the wiring structure, evaluating afringe capacitance ratio (F=C_(F)/C_(P)) according to a fringecapacitance (C_(F)) and parallel-plate capacitance (C_(P)) of the wiringstructure, and determining the wiring structure so that the fringecapacitance ratio F may satisfy the following:

$F \leq {\frac{\left( {1 - \delta_{P}} \right)\delta_{P}}{\delta_{P} - \xi_{RC}} - 1}$

The wiring structure of the second aspect suppresses the ratioΔ(RC)/(RC) within the tolerance ξ_(RC).

If each wire in the wiring structure is 1 mm or longer, the ratioΔ(RC)/(RC) greatly affects the delay time, and therefore, the secondaspect is especially effective for semiconductor devices having suchlong wires.

A third aspect of the present invention provides a method of designing awiring structure of a semiconductor device. The method includesestimating a process-originated variation ratio (δ_(P)) for the wiringstructure, setting a capacitance variation ratio (ΔC/C) andresistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiringstructure each to δ_(P)/2, evaluating a fringe capacitance ratio(F=C_(F)/C_(P)) according to a fringe capacitance (C_(F)) andparallel-plate capacitance (C_(P)) of the wiring structure, anddetermining the wiring structure so that the fringe capacitance ratio Fmay satisfy the following:F=1−δ_(P)

The wiring structure of the third aspect restricts the tolerance ξ_(C)for the ratio ΔC/C and the tolerance ξ_(RC) for the ratio Δ(RC)/(RC)each to half the ratio δ_(P).

A fourth aspect of the present invention provides a wiring structure ofa semiconductor device, having a wiring layer formed on an insulatingfilm. The width W of each wire in the wiring layer and the thickness Hof the insulating film satisfy “1≦W/H ≦6,” and the length of each wirein the wiring layer is shorter than 1 mm.

When the length of each wire in the wiring layer is shorter than 1 mm, acapacitance variation ratio ΔC/C of the wiring layer due toprocess-originated variations is a main factor to cause a delay. Thewiring structure of the fourth aspect is effective to suppress such adelay. For a multilayer wiring structure, the fourth aspect isapplicable to lower wiring layers having short wires.

A fifth aspect of the present invention provides a wiring structure of asemiconductor device, having a wiring layer formed on an insulatingfilm. The width W of each wire in the wiring layer and the thickness Hof the insulating film satisfy “W/H≦1,” or “W/H≧6,” and the length ofeach wire in the wiring layer is 1 mm or longer.

When the length of each wire in the wiring layer is 1 mm or longer, aresistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiring layerdue to process-originated variations is a main factor to cause a delay.The wiring structure of the fifth aspect is effective to suppress such adelay. For a multilayer wiring structure, the fifth aspect is applicableto upper wiring layers having long wires.

A sixth aspect of the present invention provides a wiring structure of asemiconductor device, having multiple wiring layers. The ratio W/I ofthe width W to thickness T of each wire in the first and second wiringlayers is greater than the ratio W/T of each wire in the third and upperlayers.

The length of each wire in the first and second layers is shorter than 1mm, and therefore, a capacitance variation ratio ΔC/C of these wiringlayers is a main factor to cause a delay. The length of each wire in thethird and upper layers is 1 mm or longer, and therefore, aresistance-by-capacitance variation ratio Δ(RC)/(RC) of these wiringlayers is a main factor to cause a delay. The sixth aspect is capable ofsuppressing both types of delay.

A seventh aspect of the present invention provides a wiring structure ofa semiconductor device, having first and second wiring layers and apower-supply or clock-signal wiring layer between the first and secondwiring layers.

The power-supply or clock-signal wiring layer serves as a shield plateto suppress crosstalk between the first and second wiring layers.

An eighth aspect of the present invention provides a wiring structure ofa semiconductor device, having an intermediate wiring layer sandwichedbetween a power-supply wiring layer and a clock-signal wiring layer.

The power-supply wiring layer and clock-signal wiring layer serve asshield plates to suppress crosstalk between the intermediate wiringlayer and other wiring layers.

A ninth aspect of the present invention provides a method of designing awiring structure of a semiconductor device. The wiring structureincludes copper wires each provided with a barrier metal layer along theside and bottom faces thereof. The method includes estimating aprocess-originated variation ratio (δ_(P)) for the wiring structure,setting a tolerance (ξ_(R)) for a resistance variation ratio (ΔR/R) ofthe wiring structure, and determining the wiring structure to satisfythe following:

$\frac{T_{P}}{W} \leq {0.5\left\lbrack {1 - {\delta_{P}\left( {1 - \frac{1}{\xi_{R}}} \right)}} \right\rbrack}$where T_(b) is the thickness of the barrier metal layer and W is thewidth of each copper wire.

The wiring structure of the ninth aspect suppresses the ratio ΔR/Rwithin the tolerance ξ_(R).

A tenth aspect of the present invention provides a method of designing awiring structure of a semiconductor device. The wiring structureincludes copper wires each provided with a barrier metal layer along theside and bottom faces thereof. The method includes estimating aprocess-originated variation ratio (δ_(P)) for the wiring structure,setting a tolerance (ξ_(RC)) for a resistance-by-capacitance variationratio (Δ(RC)/(RC)) of the wiring structure, evaluating a fringecapacitance ratio F (=C_(F)/C_(P)) according to a fringe capacitanceC_(F) and parallel-plate capacitance C_(P) of the wiring structure, anddetermining the wiring structure to satisfy the following:

${{\frac{\delta_{P}}{1 - {2{T_{b}/W}} + \delta_{P}}\left( {1 + \frac{\delta_{P}}{1 + F}} \right)} + \left( \frac{\delta_{P}}{1 + F} \right)} \leq \delta_{RC}$where T_(b) is the thickness of the barrier metal layer and W is thewidth of each copper wire.

The wiring structure of the tenth aspect suppresses the ratio Δ(RC)/(RC)within the tolerance ξ_(RC).

If the length of each copper wire is 1 mm or longer, the ratio ΔR/R is amain factor to cause a delay. This aspect is effective to suppress sucha delay.

An 11th aspect of the present invention provides a wiring structure of asemiconductor device, having a wiring layer formed on an insulatingfilm. The wiring layer includes copper wires each provided with abarrier metal layer along the side and bottom faces thereof. The width Wof each copper wire and the thickness H of the insulating film satisfy“0.4≦W/H≦2.”

This aspect is effective to suppress a delay if the delay is mainlydependent on the ratio Δ(RC)/(RC). If the length of each copper wire is1 mm or longer, the ratio Δ(RC)/(RC) is a main factor to cause a delay,and the wiring structure of this aspect is effective to suppress such adelay.

A 12th aspect of the present invention provides a wiring structure of asemiconductor device, having multiple wiring layers each formed on aninsulating film. The third and upper wiring layers include copper wireseach provided with a barrier metal layer along the side and bottom facesthereof. The width W of each copper wire and the thickness H of theinsulating film just under the copper wire satisfy “0.4≦W/H≦2.”

The length of each wire in the third and upper wiring layers is 1 mm orlonger, and therefore, the ratio Δ(RC)/(RC) is a main factor to cause adelay in these layers. The wiring structure of the 12th aspect iseffective to suppress such a delay.

A 13th aspect of the present invention provides a method of designing awiring structure of a semiconductor device, including findingrelationships among the cross-sectional-shape parameters of each wire inthe wiring structure to satisfy an equivalent-variations condition, anddetermining the cross-sectional-shape parameters of each wire in thewiring structure so that a capacitance variation ratio ΔC/C andresistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiringstructure may balance with each other at a given level.

The “equivalent-variations condition” is a condition to minimize theratios ΔC/C and Δ(RC)/(RC). Namely, the equivalent-variations conditionis a condition to achieve |ΔC/C|=|Δ(RC)/(RC)|. The equivalent-variationscondition has universality for a process-originated variation ratioδ_(W)/δ_(T). The equivalent-variations condition is a new concept toserve a technical index or a design criterion for evaluating the ratiosΔC/C and Δ(RC)/(RC). The equivalent-variations condition is useful toeasily determine a wiring structure that suppresses the ratios ΔC/C andΔ(RC)/(RC).

A CAD tool incorporating an algorithm for finding anequivalent-variations condition is useful to efficiently determine anoptimum wiring structure.

A 14th aspect of the present invention provides a wiring structure of asemiconductor device, having multiple wiring layers each formed on aninsulating layer and having wires each of 1 mm or longer. The dielectricconstant of an insulating layer between horizontally adjacent ones ofthe wires is higher than the dielectric constant of an insulating layerbetween vertically adjacent ones of the wires.

The insulating layer between vertically adjacent wires is an insulatinglayer formed between two wiring layers or between a wiring layer and asubstrate.

The dielectric constant of an insulating layer is a mean dielectricconstant of the insulating layer. If the insulating layer is a singlelayer, the dielectric constant thereof is the dielectric constant of thematerial of the insulating layer. If the insulating layer consists ofmultiple layers, the dielectric constant thereof is a mean dielectricconstant of the multiple layers.

The 14th aspect increases a coupling capacitance between horizontallyadjacent wires, to suppress the resistance-by-capacitance variationratio Δ(RC)/(RC) of each wiring layer.

The insulating layer between horizontally adjacent wires may have a partwhose dielectric constant is higher than that of the insulating layerbetween vertically adjacent wires, to increase a mean dielectricconstant of the insulating layer between horizontally adjacent wireshigher than that of the insulating layer between vertically adjacentwires.

Partly providing the insulating layer between horizontally adjacentwires with a material having a high dielectric constant widens aselection range of dielectric materials. The width of the material ofhigh dielectric constant is adjustable to control relationships amongthe dielectric constants of wiring layers.

This aspect is achievable by forming an insulating film having a highdielectric constant along the side wall of each wire.

According to the 14th aspect, each wire may be made of material whosespecific resistance is lower than that of aluminum (Al). This helpsreduce the aspect ratio (thickness-to-width ratio T/W) of each wire tosimultaneously suppress the Δ(RC)/(RC) and RC of the wiring structure.The material whose specific resistance is lower than that of aluminummay be copper (Cu).

A 15th aspect of the present invention provides a wiring structure of asemiconductor device, having multiple wiring layers each formed on aninsulating layer and having wires each shorter than 1 mm. The dielectricconstant of an insulating layer between vertically adjacent ones of thewires is higher than the dielectric constant of an insulating layerbetween horizontally adjacent ones of the wires.

The 15th aspect increases wire-to-ground capacitance and suppresses acapacitance variation ratio ΔC/C of the wiring structure in response toprocess-originated variations.

The insulating layer between vertically adjacent wires may partly beprovided with an insulating layer whose dielectric constant is higherthan that of the insulating layer between horizontally adjacent wires,so that a mean dielectric constant of the insulating layer betweenvertically adjacent wires becomes higher than the dielectric constant ofthe insulating layer between horizontally adjacent wires.

Since the insulating layer between vertically adjacent wires is onlypartly provided with a layer having a high dielectric constant, the 15thaspect has a wide range of dielectric materials to be selected. Thewidth of the partial layer of high dielectric constant is adjustable tocontrol relationships among the dielectric constants of wiring layers.

The wires of the 15th aspect may be made of a conductive material whosespecific resistance is lower than that of aluminum (Al). This helpsimprove the aspect ratio (thickness-to-width ratio T/W) of each wire tosimultaneously suppress the capacitance C and capacitance variationratio ΔC/C of the wiring structure. The material whose specificresistance is lower than that of aluminum may be copper (Cu).

A 16th aspect of the present invention provides a wiring structure of asemiconductor device, having an upper wiring structure and a lowerwiring structure. In the upper wiring structure, the dielectric constantof an insulating layer between horizontally adjacent wires is higherthan that of an insulating layer between vertically adjacent wires. Inthe lower wiring structure, the dielectric constant of an insulatinglayer between vertically adjacent wires is higher than that of aninsulating layer between horizontally adjacent wires.

In the upper wiring structure, the 16th aspect increases couplingcapacitance between horizontally adjacent wires, to suppress aresistance-by-capacitance variation ratio Δ(RC)/(RC) of wiring structurein response to process-originated variations. In the lower wiringstructure, the 16th aspect increases wire-to-ground capacitance, tosuppress a capacitance variation ratio ΔC/C of the wiring structure inresponse to process-originated variations.

The upper wiring structure includes the third and upper wiring layerscounted from a substrate, and the lower wiring structure includes thefirst and second wiring layers.

Any of the wiring layers may have wires whose main component is copper.If the upper wiring structure employs copper wires, the aspect ratio(thickness-to-width ratio T/W) of each wire will be decreased tosimultaneously suppress the Δ(RC)/(RC) and RC of the wiring structure.If the lower wiring structure employs copper wires, the aspect ratio(thickness-to-width ratio T/W) of each wire will be increased tosimultaneously suppress the C and ΔC/C of the wiring structure.

A given one of the wiring layers may have wires whose main component iscopper (Cu), and wiring layers above the given wiring layer may havewires mainly made of aluminum (Al). This is effective to form fine wiresof proper aspect ratio in lower wiring layers.

A 17th aspect of the present invention provides a wiring structure of asemiconductor device, having multiple wiring layers. Two wiring layersthat may cause crosstalk are separated from each other with anotherwiring layer being interposed between them.

The 17th aspect separates wiring layers that may cause crosstalk fromeach other, to suppress crosstalk and improve the reliability of thesemiconductor device.

BRIEF DESCRIPTION OF THF DRAWINGS

FIG. 1 is a graph showing relationships among the capacitance variationratio ΔC/C, resistance-by-capacitance variation ratio Δ(RC)/(RC), andfringe capacitance ratio F of a wiring structure with aprocess-originated variation ratio δ_(P) being 10%;

FIG. 2 is a sectional view showing a model of a wiring structure havingwires arranged at regular intervals;

FIG. 3 is a graph showing relationships between the capacitance C andwidth-to-insulation thickness ratio W/H of a wiring structure with avariation in W being +10% to −10%, in which a continuous line isobtained by simulations that consider fringe capacitance and a dottedline is obtained by parallel-plate approximation that considers nofringe capacitance;

FIG. 4 is a graph showing relationships between the ratios ΔC/C and W/Hof a wiring structure with a variation in W being +10%, in which acontinuous line is obtained by simulations that consider fringecapacitance and a dotted line is obtained by parallel-plateapproximation that considers no fringe capacitance;

FIG. 5 is a graph showing relationships between the ratios Δ(RC)/(RC)and W/H of a wiring structure with a variation in W being +10%, in whicha continuous line is obtained by simulations that consider fringecapacitance and a dotted line is obtained by parallel-plateapproximation that considers no fringe capacitance;

FIG. 6 is a graph showing relationships between the ratios Δ(RC)/(RC)and W/H of a wiring structure;

FIG. 7 is a graph showing relationships between the ratiosF(=C_(F)/C_(P)) and W/H of the wiring structure of FIG. 2;

FIG. 8 is a sectional view showing a model of a wiring structure havinga single wire;

FIG. 9 is a graph showing relationships between the ratiosF(=C_(F)/C_(P)) and W/H of the wiring structure of FIG. 8;

FIG. 10 is a sectional view showing a wiring structure consisting oflower first and second wiring layers having short wires to suppress ΔC/Cand upper wiring layers having long wires to suppress Δ(RC)/(RC);

FIG. 11 is a sectional view showing a wiring structure having no powersupply wires at the top thereof, to suppress crosstalk;

FIG. 12 is a sectional view showing a wiring structure that sandwiches acritical wiring layer between a power-supply wiring layer and aclock-signal wiring layer to shield the critical wiring layer andprevent crosstalk;

FIG. 13 is a sectional view showing a model of a wiring structure inwhich copper wires are arranged at regular intervals with each copperwire having a barrier metal layer along the side and bottom facesthereof;

FIG. 14 is a graph showing the difference in resistance R between acopper Wire with a barrier metal layer and a copper wire without thesame;

FIG. 15 is a graph showing relationships between the ratios ΔR/R and W/Hof a wiring structure with a variation in W being +10%;

FIG. 16 is a graph showing the difference in Δ(RC)/(RC) and W/H betweena copper wire with a barrier metal layer and a copper wire without thesame, with a variation in W being +10%;

FIG. 17 is a graph showing the universality of equivalent-variationscondition;

FIG. 18 is a log-log graph showing the equivalent-variations conditionof FIG. 17;

FIG. 19 is a three-dimensional graph showing relationships among the RC,W/H, and T/H of a wiring structure;

FIG. 20 is a two-dimensional graph showing the distribution of FIG. 19;

FIG. 21 is a three-dimensional graph showing relationships among theΔ(RC)/(RC), W/H, and T/H of a wiring structure;

FIG. 22 is a two-dimensional graph showing the distribution of FIG. 21;

FIG. 23 is a graph showing relationships among the RC, Δ(RC)/(RC), W/H,and T/H of a wiring structure;

FIG. 24 is a graph showing relationships among the RC, Δ(RC)/(RC), W/H,and T/H of a wiring structure employing copper wires;

FIG. 25 is a graph showing relationships among the RC, Δ(RC)/(RC), W/H,and T/H of a wiring structure employing copper wires and horizontalinsulating films of SiN;

FIGS. 26A to 26C are sectional views showing wiring structures havinglong wires;

FIG. 27 is a three-dimensional graph showing relationships among the C,W/H, and T/H of a wiring structure;

FIG. 28 is a two-dimensional graph showing the distribution of FIG. 27;

FIG. 29 is a three-dimensional graph showing relationships among theΔC/C, W/H, and T/H of a wiring structure;

FIG. 30 is a two-dimensional graph showing the distribution of FIG. 29;

FIG. 31 is a graph showing relationships among the C, ΔC/C, W/H, and T/Hof a wiring structure;

FIG. 32 is a graph showing relationships among the C, ΔC/C, W/H, and T/Hof a wiring structure employing copper wires and an insulating film ofSiN under the copper wires;

FIGS. 33A to 33D are sectional views showing wiring structures employingshort wires;

FIGS. 34A and 34B are sectional views showing wiring structures havingmultiple wiring layers; and

FIG. 35 is a table showing dielectric materials usable to forminsulating layers.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

The first embodiment relates to a method of designing a wiring structurein consideration of fringe capacitance.

An outline of the method will be explained. The inventors of the presentinvention have analyzed the prior arts in connection with reducing thecapacitance C and resistance-by-capacitance RC of a wiring structure andhave found that suppressing the influence of process-originatedvariations on C and RC is important.

Also clarified by the inventors is that the capacitance variation ratioΔC/C and resistance-by-capacitance variation ratio Δ(RC)/(RC) of awiring structure conflict with each other due to fringe capacitance(C_(F)) to be produced at the periphery of the wiring structure.

FIG. 1 is a graph showing relationships among the ratios ΔC/C,Δ(RC)/(RC), and F of a wiring structure with a process-originatedvariation ratio δ_(P) of 10%. Here, “F” is a fringe capacitance ratioand is equal to C_(F)/C_(P) where C_(F) is fringe capacitance of thewiring structure and C_(P) is parallel-plate capacitance of the wiringstructure. As F increases, ΔC/C is more suppressed. As F decreases,Δ(RC)/(RC) is more suppressed.

The inventors have found an equation to calculate a proper fringecapacitance ratio F for a wiring structure according to aprocess-originated variation ratio δ_(P) estimated for the wiringstructure and a tolerance ξ_(C) for a capacitance C of the wiringstructure or a tolerance ξ_(RC) for a resistance-by-capacitance RC ofthe wiring structure. To restrict ΔC/C within ξ_(C) and Δ(RC)/(RC)within ξ_(RC), F must satisfy the followings:

$\begin{matrix}{{{\text{For}{\frac{\Delta\; C}{C}}} \leq \xi_{C}},\mspace{14mu}{F \geq {\frac{\delta_{P}}{\xi_{C}} - 1}}} & (1) \\{{{\text{For}{\frac{\Delta({RC})}{RC}}} \leq \xi_{RC}},\mspace{14mu}{F \leq {\frac{\left( {1 - \delta_{P}} \right)\delta_{P}}{\delta_{P} - \delta_{RC}} - 1}}} & (2)\end{matrix}$

The fringe capacitance ratio F and a capacitance simulator are used todetermine a proper wiring structure. For a wiring structure employingshort wires, a larger F is selected to suppress ΔC/C. For a wiringstructure employing long wires, a smaller F is selected to suppressΔ(RC)/(RC).

If ΔC/C and Δ(RC)/(RC) must both be suppressed, the fringe capacitanceratio F is set to “1−δ_(P)” to suppress ΔC/C and Δ(RC)/(RC) each to halfthe ratio δ_(P). In FIG. 1 where δ_(P) is 10%, ΔC/C and Δ(RC)/(RC) areequally suppressed if F is set to F_(CRC)(=0.9) corresponding to anintersection of two curves shown in FIG. 1.

EXAMPLE 1

The first embodiment will be explained in more detail.

FIG. 2 is a sectional view showing a model of a wiring structure inwhich wires are arranged at regular intervals in a wiring layer. Thewiring layer is formed on an insulating layer that is formed on asubstrate. The wires are covered with insulating layers. “S” is a spacebetween adjacent wires, “H” is the thickness of the insulating filmbetween the wiring layer and the substrate, “T” is the thickness of eachwire, and “W” is the width of each wire. The wires are arranged atregular intervals, the “W+S” is fixed. Dimensions are normalized basedon H because two-dimensional capacitance is determined by its shape butnot by size. The ratio T/H is fixed at 0.6. Wiring capacitance C iscalculated by two-dimensional simulation.

FIG. 3 shows the relationship between the capacitance C and ratio W/H ofthe wiring structure with a variation in the wire width W being +10% to−10% due to process-originated variations. The values of C werecalculated by simulations and by parallel-plate approximation. Theparallel-plate approximation employs wire-to-ground capacitance C₂₀ andwire-to-wire capacitance C₂₁ as follows:C ₂₀/(κ_(OX)·ε_(O) ·L)=W/HC ₂₁/(κ_(O)·ε_(O) ·L)=T/SNamely, the parallel-plate approximation considers no fringecapacitance. Each capacitance value is normalized according to adielectric constant κ_(OX)·ε_(O) and wire length L. When W is large, C₂₀becomes predominant, and when W is small, C₂₁ becomes predominant. InFIG. 3, a continuous line represents nominal wiring capacitance values,and dotted lines represent wiring capacitance values when a variation ofW is +10% to −10%.

FIG. 4 shows the relationship between the ratios ΔC/C and W/H of thewiring structure with a variation in the wire width W being +10% due toprocess-originated variation. When W/H is around 2, ΔC/C is minimum. Thevalues of ΔC/C calculated by the parallel-plate approximation are alwaysabout 10%. The difference between the simulations and the parallel-plateapproximation is whether or not fringe capacitance is considered. Thefringe capacitance relaxes ΔC/C against a change in W. Namely, thefringe capacitance makes a change in ΔC/C dull against a change in W. Itis understood that W/H must be around 2 to suppress ΔC/C. Setting W/H to2, however, is the worst for the resistance-by-capacitance variationratio Δ(RC)/(RC).

FIG. 5 shows the relationship between the absolute values of the ratios|Δ(RC)/(RC)| and W/H of the wiring structure in consideration of wireresistance R. The resistance R of a wire is in inverse proportion to thecross-sectional area WT of the wire. If the wire width W is extremelylarge or small, |Δ(RC)/(RC)| decreases. Namely, if W is extremely largeor small, the wiring structure of FIG. 2 shows only a small change in|Δ(RC)/(RC)| in response to a change in W. If W/H is around 2,|Δ(RC)/(RC)| is maximum (nearly 4%). Namely, setting W/H to 2 is theworst for |Δ(RC)/(RC)|. Values of |Δ(RC)/(RC)| calculated by theparallel-plate approximation are always below 1%.

In this way, a change in the width W of a wire oppositely influences theresistance R and capacitance C of the wire. Namely, the ratios ΔR/R andΔC/C of a wire cancel each other (negative correlation). When the widthW of a wire becomes smaller, the resistance R of the wire increases andthe wire-to-ground capacitance C₂₀ decreases. When W becomes smaller,the space S between adjacent wires becomes larger to reduce thewire-to-wire capacitance C₂₁ because “W+S” is unchanged. In a simplifiedcase where the parallel-plate approximation is established, a variationof RC will be zeroed.

$\frac{\Delta({RC})}{RC} = {\frac{{\left( {R + {\Delta\; R}} \right)\left( {C + {\Delta\; C}} \right)} - {RC}}{RC} = {\frac{\Delta\; R}{R} + \frac{\Delta\; C}{C} + \frac{\Delta\; R\;\Delta\; C}{RC}}}$If the parallel-plate approximation is established, ΔR/R+ΔC/C=0.

When preparing a wiring structure having fine wires, the structuralfactors such as W, S, H, and T (FIG. 2) of each wire make Δ(RC)/(RC)increase or decrease. This is because the wiring structure involvesfringe capacitance to hinder the establishment of the parallel-plateapproximation. In the wiring structure having fine wires, the fringecapacitance relaxes ΔC/C in connection with the wire-to-groundcapacitance C₂₀ so that ΔC/C scarcely changes in response to a change inW, thereby directly providing the influence of ΔR/R. For further finewires, the wire-to-wire capacitance C₂₁ meets the parallel-plateapproximation to provide ΔR/R=−ΔC/C, thereby zeroing a change in RC.

FIG. 6 shows components of the above equation with W being increased by10%. ΔC/C is the same as that of FIG. 4. ΔR/R is simply calculated fromthe cross-sectional area of a wire, is in inverse proportion to W, andis constant. ΔR/R and ΔC/C have opposite signs to cancel each other.When W/H is around 2, ΔC/C is small due to the fringe capacitance and isunable to cancel ΔR/R, thereby increasing |Δ(RC)/(RC)|. As a result, RCvaries widely with respect to a variation ΔW in the wire width W.

The wiring structure will analytically be explained with reference toequations. The capacitance C of the wiring structure consists of aparallel-plate capacitance component C_(P) and a fringe capacitancecomponent C_(F) as follows:C=C_(P)+C_(F)=(1+F)C_(P)where F is a fringe capacitance ratio and is equal to C_(F)/C_(P).

The following two assumptions are made:

-   -   (i) A fringe capacitance variation ΔC_(F) is negligibly smaller        than a parallel-plate capacitance variation ΔC_(P) as follows:        ΔC_(F)<<ΔC_(P)

(ii) A parallel-plate variation ratio and a resistance variation ratiocancel each other, and the absolute value of a parallel-plate variationratio is equal to a process-originated variation ratio δ_(P) as follows:

$\begin{matrix}{\frac{\Delta\; C_{P}}{C_{P}} = {{- \frac{\Delta\; R}{R}} = \delta_{P}}} & (3)\end{matrix}$

Based on these assumptions, the capacitance variation ratio ΔC/C of thewiring structure is expressed as follows with the use of the fringecapacitance ratio F:

$\begin{matrix}{\frac{\Delta\; C}{C} = {\frac{\Delta\; C_{P}}{C_{P} + C_{F}} = {\frac{1}{1 + F} \cdot \frac{\Delta\; C_{P}}{C_{P}}}}} & (4)\end{matrix}$

The resistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiringstructure is expressed as follows:

$\begin{matrix}{\frac{\Delta({RC})}{({RC})} = {{\frac{\Delta\; R}{R} + \frac{\Delta\; C}{C} + \frac{\Delta\; R\;\Delta\; C}{RC}} = {\frac{\Delta\; R}{R} + {\frac{1}{1 + F}\frac{\Delta\; C_{P}}{C_{P}}\left( {1 + \frac{\Delta\; R}{R}} \right)}}}} & (5)\end{matrix}$

This is expressed as follows in consideration of the expression (3):

$\begin{matrix}{\frac{\Delta({RC})}{({RC})} = {{- \left\lbrack {1 - {\frac{1}{1 + F}\left( {1 - \delta_{P}} \right)}} \right\rbrack}\delta_{P}}} & (6)\end{matrix}$

To suppress ΔC/C and Δ(RC)/(RC) within tolerances ξ_(C) and ξ_(RC),respectively, the fringe capacitance ratio F must satisfy thefollowings:

$\begin{matrix}{{{\text{For}{\frac{\Delta\; C}{C}}} \leq \xi_{C}},\mspace{14mu}{F \geq {\frac{\delta_{P}}{\xi_{C}} - 1}}} & (1) \\{{{\text{For}{\frac{\Delta({RC})}{RC}}} \leq \xi_{RC}},\mspace{14mu}{F \geq {\frac{\left( {1 - \delta_{P}} \right)\delta_{P}}{\delta_{P} - \delta_{RC}} - 1}}} & (2)\end{matrix}$where the process-originated variation ratio δ_(P) set for the wiringstructure is as follows:δ_(P) =ΔC _(P) /C _(P) =−ΔR/RThis is a proper assumption for variations in the width W and thicknessT of each wire in the wiring structure. If δ_(P) is 0.1 (10%), thefringe capacitance ratio F must be 1 or over to realize ξ_(C)=0.05 (5%).On the other hand, the fringe capacitance ratio F must be 0.8 or belowto realize ξ_(RC)=0.05 (5%).

FIG. 1 shows relationships among the capacitance variation ratio ΔC/C,resistance-by-capacitance variation ratio |Δ(RC)/(RC)|, and fringecapacitance ratio F of a wiring structure. ΔC/C and Δ(RC)/(RC) haveopposite signs, and in FIG. 1, Δ(RC)/(RC) has a negative sign and isrepresented with absolute values. As F increases, ΔC/C decreases and|Δ(RC)/(RC)| increases. This agrees with the conclusion mentioned above.If δ_(P) is 0.1 (10%) for the wiring structure of FIG. 2, F must be 1 orabove to realize ξ_(C)=0.05 (5%). On the other hand, F must be 0.8 orbelow to realize ξ_(RC)=0.05 (5%).

EXAMPLE 2

This example relates to a wiring structure capable of simultaneouslyreducing, to some extent, the capacitance variation ratio ΔC/C andresistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiringstructure caused by process-originated variations.

The capacitance variation ratio ΔC/C and resistance-by-capacitancevariation ratio Δ(RC)/(RC) of a wiring structure contradict with eachother, and therefore, it is difficult to simultaneously suppress them.It is possible, however, to simultaneously suppress them to some extent.As shown in FIG. 1, this is realized by establishing the fringecapacitance ratio F_(CRC) corresponding to the intersection of the twocurves of ΔC/C and |Δ(RC)/(RC)|. F_(CRC) is expressed as followsaccording to the expressions (4) and (6):F _(CRC)=1−δ_(P)  (7)

At this time, the tolerances ξ_(C) and ξ_(RC) for ΔC/C and Δ(RC)/(RC)are approximated as follows if δ_(P)<<2:

$\xi_{C} = {\xi_{RC} = \frac{\delta_{P}}{2}}$

By using F_(CRC), ΔC/C and |Δ(RC)/(RC)| are suppressed to δ_(P)/2. Atthe intersection of the two curves of FIG. 1, F (F_(CRC))=0.9 and δ_(P)is 10%. Accordingly, ΔC/C and |Δ(RC)/(RC)| are each suppressed to about5%.

FIG. 7 shows the relationship between the ratios F and W/H of the wiringstructure of FIG. 2. When W/H is around 1, F is at the peak and isapproximately 1. F_(CRC) of 0.9 is attained when W/H is 0.7 or 2. W/Hbecomes 0.7 by setting, for example, W=S=0.25 μm, H=0.36 μm, and T=0.22μm.

FIG. 8 shows a model of a wiring structure having a single wire. FIG. 9shows the relationship between the fringe capacitance ratio F andwire-width-to-insulating-film-thickness ratio W/H of the wiringstructure of FIG. 8. To determine a single-wire structure that satisfiesrequired specifications, the fringe capacitance ratio F of FIG. 9 andthe expressions (1), (2), and (7) are used.

EXAMPLE 3

This example relates to a method of designing a wiring structure havinglong and short wires.

For a wire of 1 mm or longer, a delay time is determined by the productRC of the resistance R and capacitance C of the wire. For a wire ofshorter than 1 mm, a delay time is determined by RtrC, when Rtr is thetransistor ON resistance. These matters are described in M. R. Anand,“Design of optimized high performance interconnect schemes for ULSIdevices,” Ph. D. Dissertation, Waseda Univ., p. 4, 1999. Namely, it isimportant to suppress RC for a wire of 1 mm or longer, and to suppress Cfor a wire shorter than 1 mm.

For a wiring structure having wires each of 1 mm or longer, it isimportant to suppress a resistance-by-capacitance variation ratioΔ(RC)/(RC) in response to process-originated variations. For a wiringstructure having wires each shorter than 1 mm, it is important tosuppress capacitance variation ratio ΔC/C in response toprocess-originated variations.

More precisely, for a wiring structure having long wires, it isnecessary to select a small fringe capacitance ratio F to suppressΔ(RC)/(RC). For a wiring structure having short wires, it is necessaryto select a large fringe capacitance ratio F to suppress ΔC/C.

In FIG. 4, for a wiring structure having wires each shorter than 1 mm,ΔC/C is suppressed to 7% or below against a wire width variation ratio(corresponding to the process-originated variation ratio) ΔW/W of 10% bysetting “1≦W/H≦6” where W is the width of each wire and H is thethickness of an insulating film laid under the wires. In FIG. 5, for awiring structure having wires each of 1 mm or longer, Δ(RC)/(RC) issuppressed by setting “W/H≦1,” or “W/H≧6.”

EXAMPLE 4

This example relates to a method of designing a multilayer wiringstructure.

Generally, a multilayer wiring structure forms short wires in lowerlayers and long wires in upper layers. Accordingly, wires in the firstand second layers counted from a substrate are designed to suppress acapacitance variation ratio ΔC/C, and wires in the third and upperlayers are designed to suppress a resistance-by-capacitance variationratio Δ(RC)/(RC).

In FIG. 4, for wires in the first and second layers, the width W of eachwire and the thickness H of an insulating film laid under the wires areset to “1≦W/H≦6” to suppress ΔC/C. In FIG. 5, for wires in the third andupper layers, Δ(RC)/(RC) is suppressed to 3% or below by setting“W/H≦1,” or “W/H≧6.”

FIG. 10 shows a resultant multilayer wiring structure in which W/T ofeach wire in the second layer is greater than W/T of each wire in thethird layer where W is the width of a wire and T is the thickness of thewire.

EXAMPLE 5

This example relates to a method of designing a multilayer wiringstructure in consideration of crosstalk.

A multilayer wiring structure involves a problem of crosstalk due tocoupling capacitance between vertically adjacent wires. To prevent thecrosstalk, FIG. 11 shows a power-supply or clock-signal wiring layer 11interposed between wiring layers that are not power-supply orclock-signal wiring layers. The power-supply or clock-signal wiringlayer 11 serves as a shield plate to suppress crosstalk between an upperwiring layer 12 and a lower wiring layer 13.

FIG. 12 shows power-supply or clock-signal wiring layers 11 and 14 thatsandwich a wiring layer 15. The wiring layer 15 is not a power-supply orclock-signal wiring layer. In this case, the wiring layers 11 and 14serve as shield plates to suppress crosstalk related to the wiring layer15.

Second Embodiment

The second embodiment relates to a method of designing a wiringstructure employing copper (Cu) wires.

To reduce wiring resistance, wiring structures may employ copper wireshaving low specific resistance. When employing copper wires, it is usualto form a barrier metal layer along the side and bottom faces of eachcopper wire, to prevent diffusion. This is disclosed in M. T. Bohr,“Interconnect scaling the real limiter to high performance ULSI,” Tech.Dig. 1995 IEDM, p. 241.

FIG. 13 shows a model of a wiring structure employing copper wiresformed at regular intervals with each copper wire having a barrier metallayer.

When such a barrier metal layer is used for a copper wire, an effectivecross-sectional area of the copper wire is reduced. Although theresistivity of copper is almost half the resistivity of aluminum (Al).The effect of the barrier metal layer is shown in FIG. 14 and becomesclearer when the width W of a copper wire is small. A resistancevariation ratio ΔR/R of the wiring structure having copper wires isexpressed as follows:

${\frac{\Delta\; R}{R}} = \frac{\delta_{P}}{1 - {2{T_{b}/W}} + \delta_{p}}$where T_(b) is the thickness of a barrier metal layer formed on eachcopper wire and is usually in the range of 10 to 20 nm.

The ratio ΔR/R of the wiring structure having copper wires each with thebarrier metal layer is restricted within a tolerance ξ_(R) if T_(b)/Wsatisfies the following:

$\begin{matrix}{{{\text{For}{\frac{\Delta\; R}{R}}} \leq \xi_{R}},\mspace{14mu}{\frac{T_{b}}{W} \leq {0.5\left\lbrack {1 - {\delta_{P}\left( {1 - \frac{1}{\xi_{R}}} \right)}} \right\rbrack}}} & (8)\end{matrix}$

To suppress a resistance-by-capacitance variation ratio Δ(RC)/(RC) ofthe wiring structure having copper wires within a tolerance ξ_(RC),T_(b)/W and a fringe capacitance ratio F must satisfy the following:

$\begin{matrix}{{{\frac{\delta_{P}}{1 - {2{T_{b}/W}} + \delta_{P}}\left( {1 + \frac{\delta_{P}}{1 + F}} \right)} + \frac{\delta_{P}}{1 + F}} \leq \xi_{RC}} & (9)\end{matrix}$where δ_(P) is a process-originated variation ratio set for the wiringstructure.

The wiring structure of FIG. 13 will be explained in more detail. “S” isa horizontal space between adjacent wires, “H” is the thickness of aninsulating film formed under the wires, and “T” is the thickness of thewire. “W+S” is fixed, and “T/H” is fixed at 0.6. T_(b) is the thicknessof the barrier metal layer,

FIG. 14 is a graph showing the relationship between the resistance R andW/H of wires with and without the barrier metal layer. If there is nobarrier metal, R is in inverse proportion to W, i.e., R is in proportionto 1/W. If there is a barrier metal layer of T_(b)/H=0.05. R rapidlyincreases as W becomes thinner. This means that the effectivecross-sectional area of a wire rapidly decreases as W becomes thinner.

FIG. 15 is a graph showing the relationship between the resistancevariation ratio ΔR/R and W/H of each copper wire with W being increasedby +10% due to process-originated variations. As W becomes thinner, theresistance R more quickly increases than 1/W to quickly increase ΔR/R.

If the process-originated variations involve only a wire width variationΔW in the width W of each wire and if the resistance R is in inverseproportion to the cross-sectional area of the wire, ΔR/R is expressed asfollows:

${\frac{\Delta\; R}{R}} = \frac{\delta_{P}}{1 - {2{T_{b}/W}} + \delta_{p}}$where δ_(P)=ΔW/W. Accordingly, the copper wire having the barrier metallayer must satisfy the following, to restrict ΔR/R within a toleranceξ_(R):

$\begin{matrix}{{{\text{For}{\frac{\Delta\; R}{R}}} \leq \xi_{R}},\mspace{14mu}{\frac{T_{b}}{W} \leq {0.5\left\lbrack {1 - {\delta_{P}\left( {1 - \frac{1}{\xi_{R}}} \right)}} \right\rbrack}}} & (8)\end{matrix}$

To restrict Δ(RC)/(RC) within a tolerance ξ_(RC), the following must besatisfied:

$\begin{matrix}{{{\frac{\delta_{P}}{1 - {2{T_{b}/W}} + \delta_{P}}\left( {1 + \frac{\delta_{P}}{1 + F}} \right)} + \frac{\delta_{P}}{1 + F}} \leq \xi_{RC}} & (9)\end{matrix}$where δ_(P) is a process variation ratio and F is a fringe capacitanceratio.

FIG. 16 is a graph showing the relationship between the Δ(RC)/(RC) andW/H of a copper wire in the wiring structure with the capacitance C ofthe wire being calculated according to two-dimensional simulations andwith a wire width variation ratio ΔW/W due to process-originatedvariations being 10%.

If each wire is 1 mm or longer, the product RC of the resistance R andcapacitance C of the wire determines a circuit operation. In this case,it is necessary to suppress Δ(RC)/(RC). In FIG. 16, Δ(RC)/(RC) of thecopper wire having the barrier metal layer is suppressed below 4% if0.4≦W/H≦2.

A multilayer wiring structure usually has short wires in lower layersand long wires in upper layers. Accordingly, wires in the first andsecond layers in a multilayer wiring structure are designed to mainlysuppress capacitance variations, and wires in the third and upper layersare designed to mainly suppress resistance-by-capacitance variations.

Namely, copper wires each having a barrier metal layer arranged in thethird and upper layers are formed to satisfy 0.4≦W/H≦2, to suppressΔ(RC)/(RC) below 4%. Here, “W” is the width of each copper wire and “H”is the thickness of an insulating film laid under the wires.

Third Embodiment

The third embodiment relates to a method of designing a wiring structurebased on the new concept of “equivalent-variations.”

The equivalent-variations concept has been created from the analyses ofcapacitance variation ratio ΔC/C and resistance-by-capacitance variationratio Δ(RC)/(RC) of a wiring structure. The equivalent-variationsconcept has universality and provides a technical index when designing awiring structure. A wiring structure based on the equivalent-variationsconcept is capable of simultaneously suppressing capacitance C,capacitance variation ratio ΔC/C, resistance-by-capacitance RC, andresistance-by-capacitance variation ratio Δ(RC)/(RC) related to thewiring structure.

The equivalent-variations concept will be explained.

By ignoring second-order infinitesimal quantities (ΔC/C)·(ΔR/R), thecapacitance variation ratio ΔC/C and resistance-by-capacitance variationratio Δ(RC)/(RC) of a wiring structure are expressed as follows:Δ(RC)/(RC)=(ΔC/C)+(ΔR/R)

The signs of ΔC/C and ΔR/R are always opposite to each other. Acondition to simultaneously minimize |ΔC/C| and |Δ(RC)/(RC)| toestablish |ΔC/C|=|Δ(RC)/(RC)| is defined as an equivalent-variationscondition.

Since ΔC/C and Δ(RC)/(RC) always have opposite signs, theequivalent-variations condition is expressed as follows:2×ΔC/C=−ΔR/R  (11)

C_rc (ARC suppression) is defined as a condition to suppress|Δ(RC)/(RC)| below |ΔC/C|, and c_RC (ΔC suppression) is defined as acondition to suppress |ΔC/C| below |Δ(RC)/(RC)|. Then, a conditionalexpression for C_rc is 2×ΔC/C>−ΔR/R, and a conditional expression forc_RC is 2×ΔC/C<−ΔR/R.

A wire width variation ratio ΔW/W is δ_(W) and a wire thicknessvariation ratio ΔT/T is δ_(T). For example, if W varies in the range of±10%, then δ_(W)=0.1. These are expressed as follows:

${\Delta\; R} = {\frac{1}{\left( {T \pm {\Delta\; T}} \right)\left( {W \pm {\Delta\; W}} \right)} - \frac{1}{T \cdot W}}$

Accordingly, the following is established:

$\begin{matrix}\begin{matrix}{{\Delta\;{R/R}} = {\left( {\Delta\;{R/R}} \right)_{pp} - \left( {\Delta\;{R/R}} \right)_{m\; m}}} \\{= {{- \frac{\delta_{W} + \delta_{T} + {\delta_{W}\delta_{T}}}{\left( {1 + \delta_{W}} \right)\left( {1 + \delta_{T}} \right)}} - \frac{\delta_{W} + \delta_{T} - {\delta_{W}\delta_{T}}}{\left( {1 - \delta_{w}} \right)\left( {1 - \delta_{T}} \right)}}} \\{= {{- 2} \cdot \left( {\delta_{w} + \delta_{T}} \right)}}\end{matrix} & (12)\end{matrix}$where (ΔR/R)_(pp) indicates that W and T vary in a positive directiondue to process-originated variations and (ΔR/R)_(mm) indicates that Wand T vary in a negative direction due to process-originated variations.(ΔR/R)_(pp)−(ΔR/R)_(mm) provides a maximum variation (the worst case)for ΔR/R.

According to the expression (12), ΔR/R is always a fixed value, and ifsecond-order infinitesimal values are ignored, is equal to−2·(δ_(W)+δ_(T)).

A function Fn_(EV) is defined as follows:

$\begin{matrix}{{Fn}_{EV} = {{\frac{\Delta\; C}{C}} - \left( {\delta_{W} + \delta_{T}} \right)}} & (13)\end{matrix}$

The function Fn_(EV) is useful for simplification.

Namely, if Fn_(EV)>0, then C_rc, and if Fn_(EV)<0, then c_RC. Fn_(EV)=0is the equivalent-variations condition.

The following important conclusions are derived. According to theexpression (13), a variation ratio provided by the equivalent-variationscondition of Fn_(EV)=0 is equal to “δ_(W)+δ_(T).” Whenprocess-originated variations cause the wire width W to vary by ±δ_(W)%and cause the wire thickness T to vary by δ_(T)%, a variation ratioprovided by the equivalent-variations condition of Fn_(EV)=0 is equal to(δ_(W)+δ_(T))%.

The equation Fn_(EV)=0 for the equivalent-variations condition hasuniversality for δ_(W) and δ_(T). This will be explained.

The equation for the equivalent-variations condition is expressed asfollows according to the expression (11) and the expression (12):

$\begin{matrix}{{\Delta\;{C/C}} = {{- \frac{\Delta\;{R/R}}{2}} = {\delta_{W} + \delta_{T}}}} & (14)\end{matrix}$

Substitutions are made as x=W/H and y=T/H. The wiring capacitance C is afunction of only W/H and T/H. Although there is a variable S/H, it isnot considered as a variable in this explanation because a wiring pitchof “W+S” is fixed. Accordingly, C=f(W/H, T/H)=f(x, y). Then, thefollowing is established:

$\quad\begin{matrix}{{\Delta\; C_{pp}} = {{{f\left( {{x + \delta_{Wx}},{y + \delta_{Wy}}} \right)} - {f\left( {x,y} \right)}} = {{\frac{\delta\; f}{\delta\; x} \cdot \delta_{Wx}} + {\frac{\delta\; f}{\delta\; x} \cdot \delta_{Wy}}}}} & (15) \\{{\Delta\; C_{m\; m}} = {{{f\left( {{x - \delta_{Wx}},{y - \delta_{Wy}}} \right)} - {f\left( {x,y} \right)}} = {{\frac{\delta\; f}{\delta\; x} \cdot \delta_{Wx}} + {\frac{\delta\; f}{\delta\; x} \cdot \delta_{Wy}}}}} & (16)\end{matrix}$

According to the expressions (14) to (16), the following is established:

$\quad\begin{matrix}{{\delta_{W} + \delta_{T}} = \frac{\Delta\; C}{C}} \\{= \frac{{\Delta\; C_{PP}} - {\Delta\; C_{m\; m}}}{C}} \\{= {2 \times \frac{{\frac{\delta\; f}{\delta\; x} \cdot \delta_{Wx}} + {\frac{\delta\; f}{\delta\; x} \cdot \delta_{Wy}}}{f}}}\end{matrix}$

A substitution is made as Pf=δ_(W)/δ_(T), and each side of the aboveequation is divided by δ_(T) to obtain the following:

$\frac{{Pf} + 1}{2} = \frac{{{Pf} \cdot \frac{\delta\; f}{\delta\; x} \cdot x} + {\frac{\delta\; f}{\delta\; x} \cdot y}}{f}$

This equation is dependent only on the process variation ratio Pf. Thisproves that the equivalent-variations condition has universality.

The equivalent-variations condition is applicable as a criterion whendesigning a wiring structure. It is required to makeresistance-by-capacitance (RC) variations smaller than capacitance (C)variations when designing a wiring structure involving long wires. Inthis case, the designing is carried out with Fn_(EV)<0. It is requiredto make C variations smaller than RC variations when designing a wiringstructure involving short wires. In this case, the designing is carriedout with Fn_(EV)>0. It is required to evenly suppress C and RCvariations when designing a wiring structure involving wires of anaverage length. In this case, the designing is carried out withFn_(EV)≈0.

EXAMPLE 1

This example relates to a method of designing a wiring structureaccording to the equivalent-variations concept.

The example will be explained based on the wiring structure of FIG. 2involving wires arranged at regular intervals. In FIG. 2, “W” is thewidth of each wire, “S” is a horizontal space between adjacent wires,“H” is the thickness of an insulating layer formed under the wires, and“T” is the thickness of the wire. A wiring pitch, i.e., “W+S” is fixed.For primary approximation, T is normalized according to H, and noscaling is carried out because two-dimensional capacitance is determinedby shape but not by size.

The wires are made of aluminum (Al) and the insulating layer is made ofan oxide film (SiO₂).

FIG. 17 is a graph showing the equivalent-variations condition for thewiring structure of FIG. 2. FIG. 18 is a log-log graph based on thegraph of FIG. 17. Each plot corresponds to a pair of W/H and T/H thatsatisfies the equivalent-variations condition of Fn_(EV)=0.

Before the present invention, there was no technical guideline forattesting a wiring structure that may suppress ΔC/C (Q_RC) orΔ(RC)/(RC)(C_rc). In FIGS. 17 and 18, the equivalent-variationscondition of Fn_(EV)=0 serves as a boundary to separate c_RC and C_rcregions from each other. It is possible, therefore, to select optimumdesign conditions that meet requirements. As is apparent in FIGS. 17 and18, the equivalent-variations condition has universality.

The data of FIGS. 17 and 18 is obtainable by simulations and analysesand is used to determine a wiring structure that suppresses ΔC/C andΔ(RC)/(RC).

A test element group (TEG) of wires having different sizes are formed ona chip, to actually measure ΔC/C and find the equivalent-variationscondition of Fn_(EV)=0. This technique is useful to find theequivalent-variations condition for an optional wiring structure.

An algorithm for finding the equivalent-variations condition may beincorporated in a CAD tool. The CAD tool is used to extract theequivalent-variations condition for various wiring patterns, toefficiently estimate an optimum wiring structure. The wiring structurethus designed causes little variations in the characteristics thereofagainst process-originated variations.

Fourth Embodiment

The first to third embodiments relate to designing a wiring structurethat suppresses the capacitance variation ratio ΔC/C orresistance-by-capacitance variation ratio Δ(RC)/(RC) caused byprocess-originated variations. The fourth embodiment designs a wiringstructure that suppresses both the capacitance variation ratio ΔC/C andcapacitance C of the wiring structure, or the resistance-by-capacitancevariation ratio Δ(RC)/(RC) and resistance-by-capacitance RC of thewiring structure.

EXAMPLE 1

This example relates to a method of designing a Wiring structureinvolving long wires, to simultaneously suppress Δ(RC)/(RC) and RC.

A delay in an LSI circuit is mainly dependent on theresistance-by-capacitance RC of a wiring structure of the LSI circuit ifthe wiring structure involves wires equal to or longer than 1 mm.Namely, the performance of a wiring structure having long wires isdetermined by the resistance-by-capacitance RC andresistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiringstructure. Accordingly, the wiring structure must suppress RC andΔ(RC)/(RC).

A wiring structure having wires made of aluminum (Al) and insulatinglayers made of SiO₂ will be explained in terms of suppressing RC andΔ(RC)/RC).

In the following explanation, the width of each wire involves avariation ΔW of ±10% and the thickness of each wire involves a variationΔT of ±10%.

FIG. 19 is a graph showing wiring delay values for different W/H and T/Hvalues in a wiring structure. An x-axis represents T/H values, a y-axisW/H values, and a z-axis RC values. “W” is the width of each wire, “H”is the thickness of an insulating layer formed under the wires, and “T”is the thickness of each wire. The RC values are normalized according toρ·κ_(OX)·ε_(O)·L², where ρ is the resistivity of aluminum, ε_(O) is thedielectric constant of a vacuum, κ_(OX) is the dielectric constant ofSiO₂, and L is the length of each wire.

FIG. 20 is a two-dimensional projection of the three-dimensionaldistribution of FIG. 19. Contour lines of FIG. 20 indicate that W/H andT/H must be increased to reduce RC.

FIG. 21 is a graph showing the resistance-by-capacitance variation ratioΔ(RC)/(RC) of a wiring structure. An x-axis represents T/H values, ay-axis W/H values, and a z-axis −Δ(RC)/(RC) values. FIG. 22 is a graphshowing a two-dimensional projection of the three-dimensionaldistribution of FIG. 21. A line EV corresponds to theequivalent-variations condition. Contour lines of FIG. 22 show thatΔ(RC)/(RC) decreases as W/H decrease.

FIG. 23 is an overlapped view of FIGS. 20 and 22 and is usable to find awiring structure capable of simultaneously suppressing RC andΔ(RC)/(RC).

Generally, a super-high-speed LSI involves a delay of about 1 nsec for 1mm due to the resistance-by-capacitance RC of a wiring structure of theLSI. This delay corresponds to a normalized RC value of 10^(11.5) inFIG. 23 according to parallel-plate approximation for a single wirewithout considering fringe capacitance. Accordingly, it is preferable toreduce the RC value below 10^(11.5) to suppress the delay caused by RCwhen designing a wiring structure.

On the other hand, a target value of Δ(RC)/(RC) is, for example, 15% orbelow. A wiring structure that satisfies the above two requirements isin a hatched area of FIG. 23. This hatched area corresponds to W/H ofabout 4 and T/H of about 9 to 10. Any wiring structure that meets theseconditions is capable of suppressing RC and Δ(RC)/(RC) caused byprocess-originated variations.

EXAMPLE 2

This example relates to a method of designing a wiring structure havinglong copper (Cu) wires.

FIG. 26A shows a wiring structure that satisfies the conditions of thehatched area of FIG. 23. Such a wiring structure is capable ofsimultaneously suppressing RC and Δ(RC)/(RC). However, the ratio of thewidth W of a wire to the thickness T thereof is 4:9 to 4:10, to providea large aspect ratio (T/W). Any wiring pattern having a large aspectratio is not preferable for trenching and etching processes.

To solve the problem of large aspect ratio, studies have been made ondifferent wiring and insulating materials to simultaneously suppress RCand Δ(RC)/(RC) and provide a proper aspect ratio that is acceptable forthe trenching and etching processes.

A first study is to change the material of each wire of a wiringstructure from aluminum (Al) to copper (Cu) whose resistivity is smallerthan that of aluminum. Small resistivity enables the thickness T of eachwire to be thinned while keeping the same resistance value. FIG. 24 is agraph showing relationships among the RC, Δ(RC)/(RC), T/H, and W/H of awiring structure having copper wires. Copper wires have a resistivityρ_(Cu) of 1.7 μΩ·cm and aluminum wires have a resistivity ρ_(Al) of 3.0μΩ·cm, and therefore, ρ_(Cu)/ρ_(Al) is about 0.5, which is used forcalculations.

In FIG. 24, the copper wires greatly decrease RC contour lines withrespect to W/H values. As a result, a hatched area in which RC issuppressed below 10^(11.5) and Δ(RC)/(RC) below 15% becomes larger thanthat of FIG. 23. This widens the selection ranges of W/H and T/H values.Namely a process window is widen.

Any wiring structure that suppresses RC below 10^(11.5) and Δ(RC)/(RC)below 15% has W/H of about 2 to 4 and T/H of about 5 to 10, to improvean aspect ratio (T/W).

In this way, changing aluminum wires to copper wires in a wiringstructure employing long wires helps improve the aspect ratio of eachwiring pattern.

EXAMPLE 3

This example relates to a wiring structure that involves long wires andemploys different materials for insulating layers between horizontallyadjacent wires and insulating layers between vertically adjacent wires.

As mentioned above, changing aluminum wires to copper wires widens aprocess window and improves the aspect ratio of each wire. To realize anideal aspect ratio of 1:1, a study is made to replace a part of aninsulating layer from SiO₂ to SiN. Namely, an insulating layer thatdetermines coupling capacitance C₂₁ (Refer to FIG. 2) betweenhorizontally adjacent wires is formed from SiN having a high dielectricconstant.

The coupling capacitance C₂₁ between horizontally adjacent wires isdependent on the thickness T of each wire and the dielectric constant ofan insulating layer between the adjacent wires. Accordingly, increasingthe dielectric constant of the insulating layer may increase thecoupling capacitance C₂₁. This results in increasing the capacitance Cof each wire and relaxing the resistance-by-capacitance variation ratioΔ(RC)/(RC) of the wiring structure. Increasing the coupling capacitanceC₂₁ may help decrease the thickness T relative to the width W of eachwire.

FIG. 25 is a graph showing a wiring structure employing copper wires andan insulating layer made of SiN instead of SiO₂ between horizontallyadjacent wires. The dielectric constant ε(SiO₂) of SiO₂ is 3.9 and thedielectric constant ε(SiN) of SiN is 6.7. Accordingly, ε(SiN)/ε(SiO₂) ofabout 2 is used for calculations to prepare the graph of FIG. 25.

In FIG. 25, a selective range of Δ(RC)/(RC) is expanded to expand aprocess window (hatched area) of FIG. 25 larger than that of FIG. 24. Asa result, a wiring structure may have W/H and T/H values of each 5, toprovide a good aspect ratio W:T of 1:1.

FIG. 26B shows a wiring structure thus formed. Each wire 10 is made ofcopper, and an insulating film 40 between horizontally adjacent wires ismade of SiN. Other insulating layers 20 a and 20 b are made of SiO₂.

According to the prior arts, insulating layers in both the horizontaland vertical directions are made of the same material. On the otherhand, this example of the present invention employs different materialsfor horizontal and vertical insulating layers if the wiring structureinvolves wires of 1 mm or longer. Namely, the present invention formseach insulating layer between horizontally adjacent wires from amaterial having a high dielectric constant, to suppress Δ(RC)/(RC). Inaddition, the present invention employs copper wires to simultaneouslysuppress RC and Δ(RC)/(RC), to provide a good aspect ratio for eachwire.

Although this example of the present invention employs SiO₂ for aninsulating layer between vertically adjacent wires and SiN for aninsulating layer between horizontally adjacent wires, the presentinvention is not limited to these insulating materials. The same effectis achievable if a mean dielectric constant of the insulating layerbetween horizontally adjacent wires is higher than a mean dielectricconstant of the insulating layer between vertically adjacent wires.

Accordingly, there will be many combinations of insulating materials forforming these insulating layers of this example of the presentinvention. FIG. 35 is a table showing insulating materials and theirresistivity values applicable to form the insulating layers of thepresent invention.

In FIG. 26B, each insulating layer 20 for vertical insulation may bemade of FSG (Fluorine-doped Spin-on-glass) whose dielectric constant islower than that of SiO₂. In this case, each insulating layer 40 forhorizontal insulation may be made of SiO₂.

Namely, the above-mentioned effect of the present invention isachievable without using material such as SiN of high dielectricconstant. To reduce RC, it is preferable to employlow-dielectric-constant materials. For example, the insulating layer 20may be made of HSQ (Hydrogen Silses Quioxane) having a dielectricconstant of 3.2 and the insulating layer 40 of FSG having a dielectricconstant of 3.6, to further suppress RC.

The insulating layer 20 may be made of polyimide-based resin having adielectric constant of 3 or below, or a newly developed material havinga dielectric material of 2.5 or below, or a new material to be developedhaving a dielectric constant of 1.0, to reduce C and RC.

FIG. 26C shows a wiring structure having insulating layers for verticalinsulation and insulating layers for horizontal insulation whosedielectric constant is higher than that of the insulating layers forvertical insulation. Each of the insulating layers for horizontalinsulation is partly provided with an insulating film 40 b having a highdielectric constant. This structure is capable of increasing a meandielectric constant of the insulating layer, increasing couplingcapacitance C₂₁ (Refer to FIG. 2), and providing the same effect as thestructure of FIG. 26B. For example, the wiring structure of FIG. 26Cconsists of an insulating layer 20 made of SiO₂, wires 10 made of copper(Cu), and an insulating film 40 b of SiN formed on the side wall of eachwire 10. By controlling the thickness of the insulating film 40 b, it ispossible to adjust the coupling capacitance C₂₁. In this way, theinsulating layer formed between horizontally adjacent wires is notlimited to a monolayer structure. It may have a multilayer structure.

The insulating film 40 b of FIG. 26C is formed according to standardprocesses. When using a damascene method to form a wiring layer,trenches are formed on an insulating layer. The inner wall of each ofthe trenches is coated with a high-dielectric material 40 b byspattering or coating technique. Anisotropic RIE (reactive ion etching)is carried out to selectively etch the film on the bottom of each trenchwithout removing the dielectric material 40 b on the sidewall of eachtrench. Thereafter, the trenches are buried to form wires according to aknown technique.

Materials to form the insulating layer 20 and insulating film 40 b ofFIG. 26C may be selected from the table of FIG. 35 or from any othermaterials. For example, the insulating layer 20 may be made of HSQ andthe insulating film 40 b of FSG, to reduce the total capacitance C ofthe wiring structure.

EXAMPLE 4

This example relates to a method of designing a wiring structure capableof simultaneously suppressing the capacitance C and capacitancevariation ratio ΔC/C of the wiring structure.

A delay time in an LSI circuit involving wires shorter than 1 mm isdetermined by the product of a transistor ON resistance Rtr and a wiringcapacitance C. Namely, the operation of the LSI circuit is influenced bythe capacitance C and capacitance variation ratio ΔC/C of the wiringstructure of the LSI circuit. It is important, therefore, to suppressthe C and ΔC of the wiring structure that includes short wires.

A wiring structure that employs aluminum as wiring material and SiO₂ asinsulating material will be explained. The wiring structure is subjectedto process-originated variations including a wire-width variation ΔW of±10% and a wire-thickness variation ΔT of ±10%.

FIG. 27 is a graph showing the capacitance C of the wiring structurewith an x-axis representing wire-thickness-to-insulating-film-thicknessratios T/H, a y-axis wire-width-to-insulating-film-thickness ratios W/H,and a z-axis C values. The values of C are normalized according toε_(O)·L. FIG. 28 is a two-dimensional projection of thethree-dimensional distribution of FIG. 27. Contour lines of FIG. 28indicate that C is small if both the W/H and T/H values are small.

FIG. 29 is a graph showing the capacitance variation ratio ΔC/C of thewiring structure with an x-axis representing W/H values, a y-axis T/Hvalues, and a z-axis ΔC/C values. FIG. 30 is a two-dimensionalprojection of the three-dimensional distribution of FIG. 29. In FIG. 30,a line EV indicates the equivalent-variations condition. Contour linesof FIG. 30 indicate that T/H values must be reduced to suppress ΔC/C.

FIG. 31 is an overlapped view of FIGS. 28 and 30 and is usable to find awiring structure capable of simultaneously suppressing the capacitance Cand capacitance variation ratio ΔC/C of the wiring structure.

For example, a target normalized capacitance value C/(ε_(O)·L) is 7 orbelow and a target ΔC/C value is 15% or below. In this case, a hatchedarea of FIG. 31 corresponds to preferable wiring conditions. Namely, apreferable wiring structure has W/H of about 1.5 to 4 and T/H of about0.8 or below, to have small C and ΔC/C against process-originatedvariations. An example of such a preferable wiring structure is shown inFIG. 33A.

EXAMPLE 5

This example relates to a wiring structure having short wires made ofcopper (Cu) and employing different materials for insulating layers forhorizontal insulation and insulating layers for vertical insulation.

The wiring structure of FIG. 33A designed as mentioned above maysimultaneously suppress C and ΔC/C. However, if the thickness H of theinsulating film formed under the wires is fixed, a width-to-thicknessratio W:T of each wire is 4:1 to 8:1 to provide a small aspect ratio(T/W). Namely, the thickness of a wire is too small compared with thewidth thereof.

A wire having such a small aspect ratio is wide to require a large areaon a substrate. This is not preferable to form a fine LSI.

In a multilayer wiring structure, lower wiring layers usually involveshort and fine wires, and therefore, an excessively small aspect ratiois a problem. It is required, therefore, to narrow the width W of eachwire. To reduce the width W of a wire without increasing the resistanceR thereof, the material of the wire may be changed from aluminum (Al) tocopper (Cu) having lower resistivity.

If the width W of a wire is reduced without changing the thickness Tthereof, the coupling capacitance C₂₁ (Refer to FIG. 2) of the wire maydrop to reduce the total capacitance C of wiring and increase thecapacitance variation ratio ΔC/C of the wiring. Accordingly, it ispreferable to reduce ΔC/C by increasing the wire-to-ground capacitance(Refer to FIG. 2) of the wire without widening the wire.

More precisely, the material of wires is changed from aluminum tocopper, and the material of an insulating layer laid under the wires ischanged from SiO₂ to SiN. FIG. 32 shows the characteristics of such awiring structure. Although a process window (hatched area) of FIG. 32 issmaller than that of FIG. 31, SiN increases the wire-to-groundcapacitance C₂₀ and shifts the process window toward a smaller widthside. For example, a wiring structure of W/H of about 1 and T/H of about0.5 improves the aspect ratio W:T up to 2:1.

FIG. 33B is a sectional view showing the wiring structure of improvedaspect ratio. Each wire 11 is made of copper, an insulating film 50 ofSiN of high dielectric constant, and an insulating layer 21 of SiO₂. Abase layer 31 may be a lower wiring layer or a substrate.

According to the prior arts, insulating layers for horizontal andvertical insulation are made of the same material. On the other hand,this example of the present invention employs different materials forinsulating layers for horizontal and vertical insulation in a wiringstructure that contains wires shorter than 1 mm. In this example, adielectric constant of vertical insulating layer is higher than adielectric constant of horizontal wiring structure of W/H of about 1 andT/H of about 0.5 improves the aspect ratio W:T up to 2:1.

FIG. 33B is a sectional view showing the wiring structure of improvedaspect ratio. Each wire 11 is made of copper, an insulating film 50 ofSiN of high dielectric constant, and an insulating layer 21 of SiO₂. Abase layer 31 may be a lower wiring layer or a substrate.

According to the prior arts, insulating layers for horizontal andvertical insulation are made of the same material. On the other hand,this example of the present invention employs different materials forinsulating layers for horizontal and vertical insulation in a wiringstructure that contains wires shorter than 1 mm. In this example, adielectric constant of vertical insulating layer is higher than adielectric constant of horizontal insulating layer. At the same time,this example forms the wires from copper having low resistivity, tosimultaneously suppress the capacitance C and capacitance variationratio ΔC/C of the wiring structure against process-originatedvariations, as well as realizing an aspect ratio that is appropriate forfine processes.

Although this example of the present invention uses SiO₂ for insulatingfilms for horizontal insulation and SiN for insulating films forvertical insulation, the present invention is not limited to thesematerials. The same effect is achievable if a mean dielectric constantof the insulating layers for vertical insulation is higher than a meandielectric constant of the insulating layers for horizontal insulation.

FIG. 33C shows a wiring structure in which the dielectric constant ofinsulating layers for vertical insulation is higher than that ofinsulating layers for horizontal insulation. According to thisstructure, each wire 11 is made of copper, and an insulating film 50 bmade of, for example, SiN having a high dielectric constant is formed onthe bottom of the wire 11. Another insulating layer 21 is made of SiO₂like the prior art. insulating layer. At the same time, this exampleforms the wires from copper having low resistivity, to simultaneouslysuppress the capacitance C and capacitance variation ratio ΔC/C of thewiring structure against process-originated variations, as well asrealizing an aspect ratio that is appropriate for fine processes.

Although this example of the present invention uses SiO₂ for insulatingfilms for horizontal insulation and SiN for insulating films forvertical insulation, the present invention is not limited to thesematerials. The same effect is achievable if a mean dielectric constantof the insulating layers for vertical insulation is higher than a meandielectric constant of the insulating layers for horizontal insulation.

FIG. 33C shows a wiring structure in which the dielectric constant ofinsulating layers for vertical insulation is higher than that ofinsulating layers for horizontal insulation. According to thisstructure, each wire 11 is made of copper, and an insulating film 50 bmade of, for example, SiN having a high dielectric constant is formed onthe bottom of the wire 11. Another insulating layer 21 is made of SiO₂like the prior art.

With the insulating film 50 b of high dielectric constant being partlyprovided for an insulating layer for vertical insulation, the wiringstructure of this example increases the actual dielectric constant ofthe insulating layer for vertical insulation to increase wire-to-groundcapacitance C₂₀. As a result, this example provides the same effect asthe wiring structure of FIG. 33B.

By controlling the thickness of the insulating film 50 b of FIG. 33C, itis possible to adjust coupling capacitance C₂₁, too.

To form the insulating film 50 b on the bottom of each wire 11, a layerof the insulating film 50 b is formed on an insulating layer and ispatterned. A second insulating layer is formed on the insulating film 50b, trenches are formed in the second insulating layer to expose theinsulating film 50 b, and the trenches are buried with wiring materialto form the wires 11.

The insulating film 50 b may not be in direct contact with the bottom ofthe wire 11. It is sufficient if the insulating film 50 b is formed in apast of the insulating layer for vertical insulation. Also, it is notnecessary to align the insulating film 50 b with the wire 11 in a planview.

FIG. 33D shows a wiring structure having insulating layers forhorizontal insulation and insulating layers for vertical insulationwhose dielectric constant is higher than that of the insulating layersfor horizontal insulation.

The insulating film 21 for vertical insulation is made of SiO₂ and theinsulating layer 60 for horizontal insulation is made oflow-dielectric-constant material. As a result, the dielectric constantof the insulating layer 21 is relatively higher than that of theinsulating layer 60. The insulating layer 60 of low dielectric constantmay be made of FSG (fluorine-doped spin-on-glass).

This example makes the dielectric constant of the insulating layer 21for vertical insulation higher than that of the insulating layer 60 forhorizontal insulation without using high-dielectric material such asSiN. To reduce the capacitance C of wiring, it is preferable to usematerials of low dielectric constant.

The materials used for this example may be selected from the materialsof FIG. 35. For example, the insulating layer 60 may be made of HSQ(hydrogen silsesquioxane) having a dielectric constant of 3.2, and theinsulating layer 21 may be made of FSG having a dielectric constant of3.6, to reduce the total capacitance C of the wiring structure inaddition to providing the above-mentioned effect.

The insulating layer 60 may be made of polyimide-based resin having adielectric constant of 3 or below, or a newly developed material havinga dielectric material of 2.5 or below, or a new material to be developedhaving a dielectric constant of 1.0, to reduce the total capacitance Cof the wiring structure and a circuit delay time.

As mentioned above, this example forms wires with copper and increasesthe dielectric constant of insulating layers for vertical insulationrelative to that of insulating layers for horizontal insulation, tosimultaneously suppress the capacitance C and capacitance variationratio ΔC/C of the wiring structure and realize a good aspect ratioappropriate for fine processes. Since this example simultaneouslysuppresses C and ΔC/C that are main factors to cause a circuit delay, itrealizes proper circuit delay characteristics against process-originatedvariations.

EXAMPLE 6

This example relates to a multilayer wiring structure that is acombination of the examples 1 to 5.

The examples 1 to 5 provide a wiring structure having short or longwires. An actual semiconductor device, however, usually has a multilayerstructure involving both the long and short wires. A standard multilayerwiring structure forms transistors and memories directly on asemiconductor substrate, and short wires in lower layers, the lengths ofwires being gradually elongated toward upper layers.

FIG. 34A is a sectional view showing a multilayer wiring structure.Wires 10 are formed in an upper layer and wires 11 are formed in a lowerlayer. Both the wires 10 and 11 are made of copper (Cu).

The wires 11 in the lower layer are each shorter than 1 mm. Between asubstrate 31 and the wires 11, there is an insulating layer 21 a forvertical insulation made of USG having a dielectric constant of 4.1. Aninsulating layer 60 for horizontal insulation is made of HSQ having adielectric constant of 3.2. This results in increasing the dielectricconstant of the insulating layer 21 a higher than that of the insulatinglayer 60.

The wires 10 in the upper layer are each equal to or longer than 1 mm.Between a lower wiring layer 30 and the wires 10, there is an insulatinglayer 20 a for vertical insulation made of FSG having a dielectricconstant of 3.6. An insulating layer 40 for horizontal insulation ismade of USG having a dielectric constant of 4.1. This results inincreasing the dielectric constant of the insulating layer 40 higherthan that of the insulating layer 20 a. Materials for forming theinsulating layers are not limited to those mentioned above.

In each of the upper and lower wiring layers of the wiring structure,circuit delay is suppressed against process-originated variations. Inaddition, the wiring structure provides each wire with an aspect ratiothat is appropriate for fine processes. Consequently, this example meetsrequirements for fine devices and suppresses process-originatedvariations.

FIG. 34B is a sectional view showing another multilayer wiringstructure. Upper and lower wires 10 and 11 are made of copper (Cu). Thelower wires 11 are each shorter than 1 mm. The bottom of each wire 11 isprovided with an insulating film 50 b made of, for example, SiN whosedielectric constant is higher than that of SiO₂. The upper wires 10 areeach equal to or longer than 1 mm. The side wall of each wire 10 isprovided with an insulating film 40 b made of SiN. Other insulatinglayers 20 and 21 are made of SiO₂. This example provides the same effectas the example of FIG. 34A.

Materials of the insulating layers are not limited to those mentionedabove. They may be selected from the table of FIG. 35 or from othermaterials.

In an actual semiconductor device, the influence of process-originatedvariations is more severe on lower-layer wires that are finer thanupper-layer wires. Accordingly, it is possible to apply the conditionsof the present invention only to the lower-layer wires. For example,only the lower-layer wires may be made of copper, and the upper-layerwires may be made of aluminum.

A multilayer wiring structure has the problem of crosstalk betweenvertically adjacent wires. To prevent the crosstalk, the presentinvention provides a wiring structure that is designed not to verticallyclosely arrange wiring layers that may cause crosstalk between them.

The aluminum wires mentioned here may contain, in addition to a maincomponent of aluminum, other compounds. Also, the copper wires mentionedhere may contain, in addition to a main component of copper, othercompounds and may have a barrier metal layer. Wires made of otherconductive materials not mentioned here are also employable for thepresent invention.

Although the present invention has been explained with reference to thepreferred embodiments, the present invention is not limited to them, andas is apparent for those skilled in the art, allows variousmodifications. The wiring structures of the present invention areapplicable not only to LSIs but also to other devices that involvecircuit delay and delay variations resulting from fine processes.

1. A method of designing a wiring structure of a semiconductor device,comprising: estimating a process-originated variation ratio (δ_(p)) forthe wiring structure; setting a tolerance (ξ_(C)) for a capacitancevariation ratio (ΔC/C) of the wiring structure; evaluating a fringecapacitance ratio (F=C_(F)/C_(P)) according to a fringe capacitanceC_(F) and parallel-plate capacitance C_(P) of the wiring structure; anddetermining the wiring structure so that the fringe capacitance ratio(F) satisfies the following: $F \geq {\frac{\delta_{P}}{\xi_{C}} - 1.}$2. A method of designing a wiring structure of a semiconductor device,comprising: estimating a process-originated variation ratio (δ_(P)) forthe wiring structure; setting a tolerance (ξ_(RC)) for aresistance-by-capacitance variation ratio (Δ(RC)/(RC)) of the wiringstructure; evaluating a fringe capacitance ratio (F=C_(F)/C_(P))according to a fringe capacitance C_(F) and parallel-plate capacitanceC_(P) of the wiring structure; and determining the wiring structure sothat the fringe capacitance ratio (F) satisfies the following:$F \leq {\frac{\left( {1 - \delta_{P}} \right)\delta_{P}}{\delta_{P} - \xi_{RC}} - 1.}$3. A method of designing a wiring structure of a semiconductor device,comprising: estimating a process-originated variation ratio (δ_(P)) forthe wiring structure; setting a capacitance variation ratio (ΔC/C) andresistance-by-capacitance variation ratio (Δ(RC)/(RC)) of the wiringstructure each to half the estimated process-originated variation ratio(δ_(P)/2); evaluating a fringe capacitance ratio (F=C_(F)/C_(P))according to a fringe capacitance (C_(F)) and parallel-plate capacitance(C_(P)) of the wiring structure; and determining the wiring structure sothat the fringe capacitance ratio (F) satisfies the following:F=1−δ_(P).
 4. The method of claim 1 or 3, wherein: the wiring structureincludes wires that are each shorter than 1 mm.
 5. The method of claim 2or 3, wherein: the wiring structure includes wires that are each equalto or longer than 1 mm.
 6. A method of designing a wiring structure of asemiconductor device, the wiring structure having copper wires eachprovided with a barrier metal layer along side and bottom faces thereof,the method comprising: estimating a process-originated variation ratio(δ_(P)) for the wiring structure; setting a tolerance (ξ_(R)) for awiring resistance variation ratio (ΔR/R) of the wiring structure; anddetermining the wiring structure to satisfy the following:${\frac{T_{b}}{W} \leq {0.5\left\lbrack {1 - {\delta_{P}\left( {1 - \frac{1}{\xi_{R}}} \right)}} \right\rbrack}},$where T_(b) is a thickness of the barrier metal layer and W is a widthof each copper wire.
 7. A method of designing a wiring structure of asemiconductor device, the wiring structure having copper wires eachprovided with a barrier metal layer along side and bottom faces thereof,the method comprising: estimating a process-originated variation ratio(δ_(P)) for the wiring structure; setting a tolerance (ξ_(RC)) for aresistance-by-capacitance variation ratio (Δ(RC)/(RC)) of the wiringstructure; evaluating a fringe capacitance ratio (F=C_(F)/C_(P))according to a fringe capacitance C_(F) and parallel-plate capacitanceC_(P) of the wiring structure; and determining the wiring structure tosatisfy the following:${{{\frac{\delta_{P}}{1 - {2\;{T_{b}/W}} + \delta_{P}}\left( {1 + \frac{\delta_{P}}{1 + F}} \right)} + \frac{\delta_{P}}{1 + F}} \leq \delta_{RC}},$where T_(b) is a thickness of the barrier metal layer and W is a widthof each copper wire.
 8. The method of claim 6 or 7, wherein: the wiringstructure includes wires that are each equal to or longer than 1 mm. 9.A method of designing a wiring structure of a semiconductor device,comprising: finding an equivalent-variations condition forcross-sectional-shape parameters of each wire in the wiring structure;and determining the cross-sectional-shape parameters according to theequivalent-variations condition so that a capacitance variation ratio(ΔC/C) and resistance-by-capacitance variation ratio (Δ(RC)/(RC)) of thewiring structure is balanced with each other at a given level.